A power supply in a mobile computing device, such as a smart phone, is designed with multiple operating constraints in mind. One such operating constraint includes the non-constant current draw that is expected of a processing core. Specifically, generally it is expected that a processing core will draw a relatively high amount of current during a processing operation, but may be idle or nearly idle and have much lower current consumption during other times. However, abrupt changes in current consumption may cause a voltage on a voltage rail to droop.
An operating voltage provided by a voltage rail may affect the timing of various circuits in a processor core. For instance, it is generally the case that a lower supply voltage may result in somewhat slower operation of components, such as transistors. Furthermore, a processing core may have multiple critical paths, where a critical path is typically an identified path for data signals having a delay from beginning to end that is higher than that of other paths. Thus, processors are often designed with the critical paths in mind, where critical paths are considered worst-case paths that when satisfied provide assurance that the other paths have correct timing.
In some scenarios, it may be expected that a droop in supply voltage may slow transistor operation enough that timing errors may occur in one or more critical paths. Therefore, conventional processors are often designed having a higher operating voltage so that droops do not go below a voltage where timing errors would be expected to occur. However, that added operating voltage level (“voltage margin”) comes at a price of higher power consumption.
Accordingly, there is a need in the art for improved detection of voltage changes and resulting compensation of the detected voltage changes.